We discussed the priority of output pixels in a previous article. It is common to consider video output as a stack of planes, where pixels in higher-priority planes hide all those of lower priority. Pixels in Pole Position are clocked out at 6.144 MHz on the rising edge of nPIXCLK.

Characters On Top

The topmost plane of pixels in Pole Position are character tiles. Each 4-bit character pixel is registered by the nB-6M clock. An all-ones detector determines whether an instantaneous character pixel is selected or treated as transparency.

About 125ns is available for the all-ones detection and the pixel-selection multiplexers to settle before a pixel is clocked out.

Character Pixels

The character pixels are found in the 8192-by-8-bit ROM at 7N. The upper bits address selection is composed of the 8 LSBs of the CHA value (and CHA14, details below), stored at the falling edge of 4H. The value is therefore stable for eight pixels, until 4H falls again.

For those eight pixel times, the least significant ROM address bits are composed of 4H and the lowest vertical bits. The vertical position is stable for the entire period of eight pixels, only the n4H signal will switch from high-to-low after the first four pixels are clocked.

Given that the three least-significant bits of the CRT beam's vertical position are used, the characters are evidently eight pixels tall.

Namco Custom 02xx

In Pole Position, SHFT[1:0] is developed by a Namco custom chip 02xx, which shifts the upper and lower nibbles of the 8-bit character data from 7N, clocked by nB-6M.

This aligns with the application of the three least-significant bits of the horizontal beam position, consistent with the character bitmaps being eight pixels wide.

Content Of Character ROMs 7N+8M

Here is a sample extract of the eight-by-eight pixel character data from Pole Position ROMs, with a single color palette permutation. Other pallette permutations would develop different color combinations.

These character/tiles would only appear at 8-pixel boundaries within the 256 x 224 pixel display area (refer to this previous article).

CHA Generation

CHA[14:0] is simply the instantaneous value of the "playfield video memory", implemented by four 2048 byte static RAMs in a two-by-two configuration, yielding a memory space of 4096 16-bit words. The MSB of each 16-bit word does not form a part of CHA.

The system CPUs have access to this RAM over the access bus while 2H is asserted, otherwise the chips are outputting a 16-bit word based on their current address.

The shared access bus will be discussed in a future article. For now we take for granted that the addressing of these RAM chips is tied to the position of the CRT beam, and aligned such that character selection is advanced every eight pixels.

Notes On ROM 7N Size

The character format described has each 8x8 pixel character composed of two bits per pixel. The memory therefore is consumed at 16 bytes per character.

The character ROM at 7N is wired for 13 bits, addressing 8192 bytes. However, classic Pole Position populates a 4096 byte ROM at 7N. Therefore it will ignore the most-significant address bit, and emit two identical character sets regardless of the state of CHA_14. Although the hardware supports a 512-character set, a 256-character set, in duplicate, is present in Pole Position.

Next Article

Next time we dig into more detail of CHA generation and look at the lowest-level pixel plane.